San Jose, Calif. — Aimed at advanced product applications that call for small form factors and low-power consumption, Novellus Systems and IBM Corp. are working on a joint development program (JDP) to design a copper-based 3-D semiconductor through-silicon via (TSV) process leveraging Novellus’ SABRE copper electroplating and VECTOR plasma-enhanced chemical vapor deposition (PECVD) systems. The goal of the program is to develop a highly reliable and cost-effective manufacturing process that will enable the 3-D integration of multiple semiconductor chips for advanced product applications.
Novellus said there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to the ever-shrinking mobile device designs that require smaller components. Stacking multiple chips together in a “sandwich-like” structure and connecting all layers together with conductive copper vias allows the final module to be smaller in size through an increase in volumetric circuit density, explains the company.
In addition, the short interconnect length between each chip increases device speed and consumes less power. The stacked chip structure also allows for a greater range of device-specific functions, including heterogeneous integration, to meet the needs of today’s mobile devices including cell phones, PDAs, and laptop computers.
Although there are many benefits to using TSV, there are also several key challenges related to integrating TSVs into semiconductor manufacturing processes so that the new structure is both highly reliable and cost effective, which the new joint program will address.
One of the integration challenges is reducing the excess deposition of copper or “overburden” while achieving void-free fill of the extremely deep, high aspect ratio structures, where the overburden thickness varies as a function of TSV geometry, said Novellus. Another integration challenge requires the ability to deposit lower temperature dielectric films during the TSV manufacturing sequence so that the wafer thermal budget limit is not exceeded, according to the company.
Novellus said its SABRE Electrofill TSV process reduces copper overburden by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. SABRE’s optimized TSV chemistries are also said to have faster plating times, resulting in higher throughputs.
To address the requirement of lower temperature dielectrics, Novellus said its VECTOR platform enables the deposition of stable dielectric films at temperatures less than 200 degrees C with the breakdown voltage, leakage performance, and wafer-to-wafer repeatability required for reliable, high yielding TSVs.
Together, the SABRE and VECTOR applications are said to simplify the TSV manufacturing process and enable cost-effective, high-performance 3-D chip integration for a broad range of applications. Novellus and IBM are evaluating and further developing the Novellus processes in IBM’s 3-D integration program.
Other partnerships also are cropping up around 3-D TVS in the industry. For example, IMEC and Synopsys announced a similar partnership last week (Mar. 10) to develop 3-D stacked IC technologies.
See related articles:
IMEC, Synopsys partner on 3-D stacked IC development
Part 1 of 3: Trends in advanced IC packaging
Alchimer: 20:1 through-silicon vias save chip makers $700 per 300-mm wafers