Aurora, Ill. Connor-Winfield has introduced its STC5420 series of timing chips for SDH/SETS, SONET and Synchronous Ethernet networking applications. The single-chip clock synchronization solutions are fully compliant with ITU-T G.813 option 1 and 2 and Telcordia GR1244 and GR253.
The RoHS 6/6 compliant timing chip family accepts 12 clock reference inputs from 8 kHz to 125 MHz in LVPECL, LVCMOS or LVDS and generates 10 synchronized clock outputs from 2 kHz to 312.5 MHz in LVCMOS, LVPECL or LVDS. The synchronized outputs may be programmed for a variety of frequencies including Nx8kHz, OC-n, Ethernet frequencies and framing pulse clocks. Reference inputs are individually monitored for activity and quality, and reference selection may be manual, fast-manual or automatic.
Independent timing generators operate in freerun, synchronized, pseudo-holdover and holdover mode. Each timing generator includes a DSP-based PLL. SDP-based PLL technology eliminates the need for any external parts except the 12.8-MHz oscillator.
Other key features include support for master/slave and multiple master redundant applications, programmable compensation for phase delay between master and slave unit in 0.1 ns steps, and phase align or hitless reference locking/switching. It also offers a programmable loop bandwidth from 0.1 Hz to 100 Hz, and supports Intel, Motorola, Multiplex and SPI bus interfaces.
The STC5420 product line also offers a smaller TQ64 package configuration option (p/n STC5425) as well as part number configurations that allow for reduced functionality and lower cost.
Pricing: $35 at 1K.