European ASIC and system-on-chip (SoC) purchasers can now take advantage of electrical programmable fuse (eFUSE) technology when developing ICs, says the ASIC and Foundry Business Unit at Toshiba Electronics Europe (TEE).
The eFUSE technology uses electrically programmable PMOS gate oxide anti-fuses to provide a flexible, cost-efficient and easy-to-use solution for performance tuning, memory repair and the updating of configuration and version data. eFUSE can also be used for chip ID memory and tracing functions and key ROM storage for secure data transmission. Read operation requires only the core IC power supply, while the high programming voltage required for write operations is provided by an integrated program voltage generator from an external 2.5V or 3.3V supply.
Fully compatible with Toshibas latest CMOS technologies, eFUSE is supplied with customer-selected configurations as a fully integrated one-time-programmable (OTP) macro. Programming can be performed either by the customer (i.e.. in the field) or by Toshiba during IC testing. Customers can specify memory content or provide algorithms for content generation.
Toshiba is offering three types of eFUSE. Generic eFUSE-SR, available for 65nm, 90nm and 130nm processes, offers serial access and a capacity of 64bit to 1kbit in 64bit increments. For 40nm and 65nm processes eFUSE-MX features random access and capacities up to 8kbit. Finally, for 40nm technologies eFUSE-SS is a small capacity, 16bit macro ideally suited to trimming and ID functions. In all cases Toshibas local ELDEC (European LSI Design and Engineering Centre) engineers can provide support on the implementation and use of eFUSE.
Eugen Pfumfel, the manager for ASIC and Foundry business development at Toshiba Electronics Europe comments: Adding eFUSE technology to our comprehensive range of processes and IP solutions further strengthens our offering for ASIC customers. eFUSE is flexible, cost-efficient and easy-to-use and can be integrated without additional process steps. Local design support includes models for all major EDA platforms as well as technical collateral and access to ELDEC engineers.