Get to the core of control

Described as one of the smallest and lowest power licensable 32-bit architectures on the market, Tensilica’s Xtensa 8 customisable dataplane processor cores (DPUs) are ideal for high-volume SOC products. Tensilica introduced the Xtensa 8 customizable processor, the eighth generation of its market leading low-power dataplane processor cores (DPUs). The Xtensa 8 processor core starts at a size of just 15,000 gates, consuming less than 0.05mm2 in 40nm process technology making it one of the smallest licensable controller cores on the market. With power dissipation starting at just 12 W/MHz, its also one of the lowest power licensable 32-bit architectures.

Designers using an Xtensa 8 DPU can select from an expanded library of pre-verified configuration options to get the exact functionality they need. Enhancements in this new generation processor include pairs of 32-bit GPIO (general purpose input/outputs) and 32-bit Queue interfaces for direct connection to RTL (register transfer level) blocks, and a low-area, double-precision floating point accelerator.

Xtensa 8 continues our tradition of providing the unique capabilities designers require for dataplane applications, stated Steve Roddy, Tensilicas vice president of marketing and business development. The Xtensa 8 processors tiny size and low power consumption makes it ideal for high-volume SOC products in a wide range of applications including mobile phones and other portable electronic devices, digital TV, broadband set-top boxes, computer, storage, networking and communications equipment. With the tiny size of these DPUs, modern, low-cost SOCs for these markets routinely include a dozen or more programmable controllers and DPUs on one chip.

Tensilicas previous generation Xtensa processors have been licensed by over 160 companies, including five of the top 10 semiconductor companies. These DPUs have been customized and used as controllers as well as for complex functions such as communications DSPs (digital signal processors), audio, video, graphics, printers, and packet processing.

Choose Power, Area and Performance Sweet Spots

Because the Xtensa 8 processor core can be customized, designers have a wide range of choices available to meet area, power and performance requirements. Full synthesis scripts are provided for all major EDA vendors allowing designers to target their favorite libraries and processes. A typical small configuration (similar to Tensilicas Diamond Standard 106Micro with an iterative 32×32 multiplier, separate instruction and data memory interfaces, an interrupt controller with 15 interrupts at two priority levels, an integrated timer, on-chip debugging hardware, and embedded trace support) consumes just 17 W/MHz of power while occupying a mere 0.046 mm2 in TSMC 40LP process technology. That same configuration, synthesized for maximum performance in the same process technology, can run up to 540 MHz and still only consumes 25 W/MHz of power with an area of 0.074mm2.

Direct Connectivity to RTL

The Xtensa 8 processor core can be customized with new configuration check-box options that provide control and data input/output capabilities that entirely bypass the main system bus. This allows direct connectivity to blocks of RTL in the SOC, providing fine-grained, low-latency control of those hardware blocks. These connections also allow Xtensa 8 DPUs to stream data to RTL blocks at much higher speeds to dramatically improve system performance.

The 32-bit GPIO (general-purpose input output) interface provides 32 bits of input and 32 bits of output control and status information exchange that are naturally accessed directly as registers from the processors regular instruction set. This interface is ideal for peripheral control and monitoring.

The 32-bit input and 32-bit output Queue interfaces operate like FIFO (first in, first out) interfaces, providing a high-bandwidth and low latency mechanism for streaming data to and from other blocks in the system or other Xtensa processors. To the programmers viewpoint, input and output queue data is register based for simple and quick access – there is no need to load or store the data before and after any computation.

Additional Pre-Defined Function Blocks

Tensilica added a lightweight, double precision floating-point acceleration (FPA) option. It is small in area, consuming less than 7K gates, and helps significantly speed up any applications that require high-precision, low-bandwidth data operations, such as in motor control or GPS software stacks. This acceleration option is provided in addition to the existing single precision FPU (floating point unit) option.

Tensilica also added enhanced SOC infrastructure choices, including AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks, and synchronous/asynchronous reset capabilities.

Fully Backward Compatible with Earlier Versions

Tensilicas Xtensa processor cores are completely backwards compatible, meaning that code written for the first generation Xtensa processors will still run on the new Xtensa 8 processor. This allows designers to quickly migrate to new versions in order to take advantage of the power savings, performance improvements and additional functionality.

The Xtensa 8 customizable processor will be available in late October 2009.