PCIe made easy

Xilinx Spartan-6 FPGAs comply with the PCI Express 1.1 specification, supporting low-risk implementation of serial connectivity in consumer, automotive, wireless, and other price-sensitive or high volume markets. Spartan-6 FPGAs satisfy the cost, ease-of-use, and low power requirements of developing systems compliant with PCIe for applications such as in-vehicle infotainment, flat-panel displays, and video surveillance.

The integrated Endpoint block for PCI Express in Xilinx Spartan-6 LXT FPGAs has passed PCI-SIG compliance and interoperability testing for PCIe 1.1 single-lane configurations. This latest milestone underscores Xilinxs leadership in driving FPGA support for the widely adopted serial interconnect standard, and comes less than one quarter after PCI-SIG compliance of Virtex-6 FPGAs for PCIe 2.0 multi-lane configurations. Xilinx was the first to integrate compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 FPGA family, and the first to introduce a FPGA offering compliant with the 5Gbps version of PCIe 2.0 standard with soft IP support in Virtex-5 FXT and Virtex-5 TXT devices.

With the ubiquity of PCIe, system developers across the full spectrum of markets and applications are looking to Xilinx FPGAs for flexible connectivity solutions with proven low-power, low-cost silicon, said Tom Feist, senior marketing director for ISE Design Suite at Xilinx. Our Spartan-6 FPGAs provide the lowest cost PCIe implementation for programmable devices with twice the capability and less than half the power of previous Spartan-3 generation two-chip offerings. Developers can now design PCIe compliant systems based on the connectivity requirements of their applications and not be constrained by the cost of silicon.

Production-proven PCIe Implementation
PCIe 1.1 is implemented in Spartan-6 LXT devices with production-proven Xilinx GTP serial transceivers capable of up to 3.125Gbps and the LogiCORE solution using the integrated Endpoint block for PCI Express. The configurable PCIe core with physical layer (PHY) is the lowest-cost, single-lane integrated programmable implementation available today. The GTP serial transceivers are fully characterized across process, voltage, and temperature (PVT). The complete PCI-SIG compliance report is available for download.

The Spartan-6 FPGA integrated Endpoint block for PCI Express incorporates many easy-to-use features to simplify the design process as well as configurations optimized for PCIe Endpoint applications. It is also supported with additional design resources for creating complete PCIe solutions.

Design Support Available Today
Designers can immediately begin the evaluation and design of low-cost, low-power PCI Express 1.1 compliant systems with the Spartan-6 FPGA SP605 Evaluation Kit. The Xilinx CORE Generator system in the ISE Design Suite 11 delivered with the kit enables designers to configure the PCIe Endpoint block for their applications. It comes complete with reference design and all the scripts, basic testbench, and simulation models needed to streamline verification with customer designs. Designers can download at no charge the ISE WebPACK software or trial version of the full featured ISE Design Suite from the Xilinx web site.