Actel announces availability of RTAX-DSP prototype FPGAs, speeding time to market for space-flight designs.
The prototype devices will enable hardware demonstration and timing validation of designs targeted to Actels RTAX-DSP space-flight FPGAs. The newly available RTAX-DSP prototype devices have the same pin assignment, mechanical footprint and identical timing properties across the full military temperature range (-55C to 125C) as their space-qualified counterparts.
RTAX-DSP space-flight FPGAs add embedded radiation-tolerant multiply-accumulate blocks to the tested and proven industry-standard RTAX-S product family. The result is a dramatic increase in device performance and utilization when implementing arithmetic functions, such as those encountered in hardware DSP algorithms, without sacrificing reliability or radiation tolerance.
The availability of RTAX-DSP prototype FPGAs enable designers to demonstrate their RTAX-DSP designs in hardware across the full operational temperature range, said Ken O’Neill, director of high-reliability marketing for Actel. With the availability of these prototype devices, the RTAX-DSP program has achieved another important milestone in providing the high performance combined with high reliability needed by designers of signal processing systems for space-flight applications.
Providing a flexible alternative to expensive radiation-hardened ASICs, RTAX-DSP FPGAs feature up to 120 multiply-accumulate DSP mathblocks, protected against radiation-induced single event upsets (SEU) and single event transients (SET). The RTAX-DSP FPGAs use the same 0.15 m UMC wafer fabrication process and the same antifuse programmable interconnect technology that are used in the industry-standard RTAX-S FPGA family, which is now accumulating space-flight heritage on as many as nine space programs.
RTAX-DSP FPGAs offer high performance at densities of up to four million equivalent system gates and 840 user I/Os for space-based applications. The embedded DSP mathblocks feature 18 bit x 18 bit multiply-accumulate blocks enabling efficient implementation of DSP building blocks, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transforms (FFT). Each mathblock is capable of operating at 125 MHz across the full military temperature range.
The RTAX-DSP family of FPGAs is fully supported by the Actel Libero Integrated Design Environment (IDE). From design, synthesis and simulation, through floorplanning, place-and-route, timing constraints and analysis, power analysis and program file generation, Libero IDE manages the entire design flow quickly and efficiently.