Ultra high-performance MIPS64 architecture powers cavium’s new multi-core processors

1- to 48-core OCTEON® III Processors Demonstrate Continued Strength of MIPS® Architecture in 64-bit Embedded Market

MIPS Technologies, a leading provider of industry-standard processor architectures and cores for digital home, networking and mobile applications, announced that its MIPS64® architecture is powering the new 28nm OCTEON® III MIPS64 family of multicore processors from Cavium, a leading provider of semiconductor products that enable intelligent processing for networking, communications, and the digital home. OCTEON III processors are designed for the enterprise, data center, access and service provider markets, which require increasing support for converged data, voice and video. To address this need, the OCTEON III family introduced today by Cavium integrates 1 to 48 MIPS64 cores at up to 2.5GHz, providing up to 120GHz of 64-bit compute power per chip.

Cavium’s previous generation OCTEON II processor family was recently named “Best Embedded Processor” of 2011 by The Linley Group. The OCTEON III family builds upon this award-winning product, incorporating more cores and features to address markets including cloud computing, high-end core and edge routers, metro Ethernet, enterprise switches, 3G/4G/LTE base-stations, enterprise security gateways and appliances, storage networking and mobile core infrastructure equipment.

“Leveraging the industry-standard MIPS64 architecture and its broad ecosystem built over more than 20 years, we are delivering groundbreaking processors with an unprecedented level of compute power using a standard ISA. We surpassed the world’s highest CoreMark Benchmark Score for standards-based processors with our OCTEON II family in 2011, and we continue to deliver leading-edge performance with the release of our OCTEON III processors. These processors are proliferating across tier-one companies who recognize the unique value of our processors in this new era of terabit computing,” said Rajiv Khemani, Chief Operating Officer, Cavium.

“Cavium is keeping one step ahead of the industry’s appetite for ever-more sophisticated multi-core processor technologies capable of processing increasingly large amounts of data. We are pleased that Cavium continues its innovation around the 64-bit MIPS architecture, which has been the basis of a wide range of networking equipment, servers and other equipment since 1991. As data traffic increases across wired and mobile networks for streaming media, cloud computing and storage networking, companies are increasingly looking to the MIPS architecture to provide the high performance and efficiency needed for the next generation of products,” said Sandeep Vij, President and CEO, MIPS Technologies.

With the OCTEON III family, multiple chips can be combined into a single logical high-performance processor using Cavium’s innovative new chip interconnect architecture. All OCTEON III processors also incorporate new dedicated hardware engines to speed search, protocol parsing and traffic management, as well as enhanced cryptography, compression and deep packet inspection engines. For more information about OCTEON III, visit:

The MIPS64 architecture sets a new performance standard for 64-bit MIPS-Based™ embedded processors. By incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs and providing an upgrade path from the MIPS32® architecture, the MIPS64 architecture provides a solid high-performance foundation for future MIPS processor-based development. A broad and mature infrastructure and ecosystem around the MIPS64 architecture, including operating systems, middleware, development tools and more, provides MIPS64 licensees with clear benefits for 64-bit applications.