Timing and power analysis in flash-based FPGAs from Microsemi SoC

Also this summer MSC presents Microsemi Hands-on workshops with the theme “timing and power analysis in Flash-based FPGAs from Microsemi SoC”. The following dates and locations are provided for this purpose: 26th of June 2012 in Munich, 28th June 2012 in Jena and 14th of August 2012 in Quickborn (Hamburg).

In these workshops, foundations and definition of timing parameters, the power analysis and optimization of an FPGA design will form the main theme. The practical exercises can be carried out directly on your laptop with the preinstalled Libero-Software. Resulting questions are addressed directly.

Key words such as min/max clock, Pin2Pin delay, False-path, multi-cycle path, clock skew, and I/O delay are subjects of the workshops just as the analysis of the simulation examples generated from timing reports.

The workshops will be held between 10.00 – 17.00 h. Registration under:, phone/fax +49-89-945532-20/ +49-89-945532-91 or by e-mail at

The seminar will be held by experts from the MSC Vertriebs GmbH in German with English slides and costs 75 € + VAT inclusive food + DVD seminar. For the hands-on exercises, a laptop is needed.

For more information: