Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that ON Semiconductor has adopted Virtuoso® Layout Suite for Electrically Aware Design (EAD) for real-time electrical analysis of parasitic and electromigration impact on its custom physical design implementation flow. With Virtuoso Layout Suite EAD, ON Semiconductor circuit and layout designers will be able to significantly reduce design time and improve the energy efficiency of their designs by immediately seeing the impact of layout decisions on circuit performance.
“As the premier supplier of high-performance silicon solutions for energy-efficient electronics, ON Semiconductor believes it is important that we continue to enhance our design flows to keep pace with our customers’ demands for lower power consumption and faster time to market,” said Martin Kejhar, senior technical staff engineer and scientist at ON Semiconductor. “Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.”
Virtuoso Layout Suite EAD is a unique, patented in-design electrical verification capability that enables design teams to monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the design specifications. It allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance.