Cadence Design Systems, Inc., a leader in global electronic design innovation, and Semiconductor Manufacturing International Corporation, mainland China’s largest and most advanced semiconductor foundry, today jointly announced that SMIC has adopted the Cadence digital tool flow for the new SMIC Reference Flow 5.1, a complete RTL-GDSII digital flow for low-power designs. The Cadence flow incorporates advanced features to help mutual customers improve power, performance and area for 40nm chip design. Cadence tools used in the flow are RTL Compiler, Encounter Digital Implementation System, Encounter Conformal Low Power, Cadence QRC Extraction, TempusTM Timing Signoff Solution, Encounter Power System, Physical Verification System, and Cadence CMP Predictor.
SMIC’s new Reference Flow 5.1 supports Cadence Clock Concurrent Optimization (CCOpt) technology, a key feature of the Cadence Encounter Digital Implementation System. The qualification process demonstrated that, compared to traditional clock tree synthesis, CCOpt can improve power by 14 percent, area by 11 percent and performance by 4 percent on SMIC’s 40nm process.