In this article, ECIA’s president and CEO David Loftus demonstrates its commitment to helping industry understand the complex factors that affect component lead times, especially critical semiconductors.
During the pandemic, there was widespread confusion about component lead times. Customers grew frustrated about how order confirmations could differ, sometimes dramatically, from published lead times. It is critical for customers to understand factors impacting lead times and use this information effectively to properly manage their inventory.
Maintaining a balance between manufacturing output and global demand is an extraordinarily complex and difficult challenge that often causes extended product cycle time and capacity constraints.
Understanding semiconductor product manufacturing
One distinction helping to explain the confusion that regularly occurs during disruptions is the difference between ‘lead time’ and ‘cycle time’. Lead time is an estimate from the channel based on the amount of finished components sitting as inventory within the supply chain and many other factors, which will be explored below. Cycle time is how long it takes to make the component.
Semiconductor products are ‘fabricated’ on a circular slice of crystalline material referred to as a ‘wafer’. Wafers are batch processed in lots usually consisting of up to 25 wafers. Several identical semiconductor products are printed in a tiled pattern across each wafer. The wafer moves through successive processing recipes (steps) including photolithography, etch, ion implantation and deposition, to create a pattern of functional electronic devices. The number of steps depends on the product’s complexity. Simple devices such as diodes and discrete transistors can be manufactured with relatively low step counts, while high performance processors and high-density memory require high to very high step counts. The industry commonly refers to ‘mask layers’ as a measure of complexity. Thus, semiconductor process complexity can vary from six to 10 mask moves for relatively simple products like discrete diodes and transistors, to 100-plus mask layers for the highest performance processors and memory products.
After the wafer manufacturing process, devices must be singulated and assembled in packages. Dicing involves precision sawing to separate each tile on the wafer. These devices are then assembled in packages which route and connect the device to the outside world.
Understanding semiconductor manufacturing cycle times
Manufacturing cycle times can run from an average of 12 weeks to upwards of six months depending on complexity of the fab process, backend assembly and test, plus transportation between steps.
Fab cycle time is the time it takes to process a wafer lot in a fab from start to finish. It correlates directly with the complexity of the semiconductor process. Final assembly and test can add an additional four to eight weeks.
The process technology node (typically expressed in nm) refers to the size of the transistors and complexity of the electronic system on the chip. As technology advances, nodes become smaller, enabling more transistors to fit onto a single chip and improving integrated functionality, performance and efficiency. However, smaller nodes often require more advanced and precise manufacturing techniques, thereby potentially increasing the cycle time due to complexity and yield challenges.
The number of layers in a semiconductor chip also impacts its manufacturing cycle time. A 28nm device may have 40 to 50 mask layers. In comparison, a 5nm device could have 100 layers. Generally, a common metric for fab cycle time is ‘days per mask layer’. On average, a fab takes one to 1.5 days to process a layer. So, using today’s lithographic techniques, the cycle times are increasing from roughly 40 days at 28nm, to 100 days at 5nm. To complicate matters, the fab cycle time increases at the start of a process but drops as the technology matures. During the process, though, cycle times can be impacted by variability issues in the fab. The biggest hit involves the wait times between processing steps.
Capacity constraints and peak demand
Capacity constraints within semiconductor fabs and backend assembly and test facilities present another critical challenge. Fabs operate at maximum capacity thresholds, dictated by their physical space, equipment capabilities and workforce availability. During periods of peak demand—often triggered by new product releases, seasonal fluctuations, or geopolitical events—these constraints intensify, leading to potential allocation of manufacturing capacity.
Allocation occurs when semiconductor product demand exceeds manufacturers’ supply. During periods of allocation manufacturers generally prioritize certain customers or product lines based on manufacturers’ contractual and strategic considerations. This can result in delays for other customers with pending orders, impacting production timelines and ultimately affecting market competitiveness and customer satisfaction.
The long-term solution to allocation generally requires either significant reconfiguration of manufacturers’ capacity or, more likely, capital investment to increase capacity. Unfortunately, lead time recovery from a period of allocation can take on the order of years when additional equipment and wafer manufacturing clean room facilities are required. Therefore, proactive management of order backlog becomes essential to mitigate such risks and ensure timely and consistent delivery of semiconductor products.
Impact of inventory
Additional factors can affect lead times, including order quantities and channel choice. Most orders are fulfilled in less time than a full manufacturing cycle due to inventory at different points of the supply chain. For example, small to medium quantities can often be serviced from finished goods inventory in the distribution channel. Authorized distributors are experts at monitoring order patterns, economic conditions and upstream supply constraints to buffer inventory for their customers. When an order quantity exceeds available distributor stock, orders can often be serviced from a manufacturer’s finished goods or die bank, incurring only back-end assembly into packages, final test and shipping times. If insufficient die bank exists, work-in-process may also allow delivery faster than full cycle times. Large orders, orders of less popular SKUs or orders for products with no staged inventory points often require full cycle times, fab through backend. And in periods of allocation and fabs running at capacity, fab queue times for wafer starts and increased days per layer in fab can significantly stretch lead times for customers.
Importance of managing order backlog
Effective management of order backlog lets customers navigate the complexities of the semiconductor supply chain more efficiently. By closely monitoring their orders and collaborating closely with semiconductor suppliers and distributors, customers can mitigate supply chain risks, optimize inventory levels and enhance relationships with suppliers.
